In the process of fabricating modern semiconductor integrated circuits (ICs), it is necessary to form conductive lines or other structures above previously formed structures. However, prior structure formation often leaves the top surface topography of the in-process silicon wafer highly irregular, with bumps, areas of unequal elevation, troughs, trenches and/or other surface irregularities. As a result of these irregularities, deposition of subsequent layers of materials could easily result in incomplete coverage, breaks in the deposited material, voids, etc., if it were deposited directly over the aforementioned highly irregular surfaces. If the irregularities are not alleviated at each major processing step, the top surface topography of the surface irregularities can become even more irregular, causing further problems as layers stack up in further processing of the semiconductor structure.
Depending upon the type of materials used and their intended purposes, numerous undesirable characteristics are produced when these deposition irregularities occur. Incomplete coverage of an insulating oxide layer can lead to short circuits between metallization layers. Voids can trap air or processing gases, either contaminating further processing steps or simply lowering overall device reliability. Sharp points on conductors can result in unusual, undesirable field effects. In general, processing high density circuits over highly irregular structures can lead to very poor yield and/or device performance.
Consequently, it is desirable to effect some type of planarization, or flattening (levelling), of integrated circuit structures in order to facilitate the processing of multi-layer integrated circuits and to improve their yield, performance, and reliability. In fact, all of today's high-density integrated circuit fabrication techniques make use of some method of forming planarized structures at critical points in the fabrication process.
Planarization techniques generally fall into one of several categories:
1. Purely mechanical polishing (or abrading) techniques, wherein an abrasive is used to planarize the surface;
2. Chemical/mechanical (chemi-mechanical, chem-mech) polishing techniques, wherein a slurry of abrasive and a chemical, such as KOH (potassium hydroxide) is used;
3. Leveling the top surface with a filler material, then wet (chemical) or dry (plasma) etching back the filler and irregularities; and
4. Reflow techniques requiring spinning and/or elevated temperatures.
Different techniques may be selected depending on the material being levelled (planarized), and the particular stage of IC fabrication at which the planarization is performed. One feature that the various techniques have in common, however, is a general need to know when planarization is complete. Else, it can be allowed to proceed too far, removing underlying material which is intended to be planarized rather than removed (unacceptably thinned).
Consider, for example, the case of etching to planarize an irregular semiconductor layer. An overlying, sacrificial layer (e.g, photoresist, glass) may be applied using spin-on or reflow processes, in which the overlying layer tends to flatten (planarize) itself. The wafer is then either wet or dry etched with an etchant that removes the overlying layer and elevated points of underlying layer (as they become exposed) at a uniform rate. In this manner, the two layers are thinned uniformly and planarly, including the "mountains" (elevated irregularities) of the underlying irregular layer, until a smooth, flat (planarized) surface remains on the underlying layer. Etching must stop at this point--the "endpoint" of the process.
U.S. Pat. No. 4,491,499, incorporated by reference herein, discloses a method for determining the optimum time at which a plasma etching operation should be terminated, based on optical emissions in the plasma.
U.S. Pat. No. 4,312,732, incorporated by reference herein, discloses another method for monitoring plasma discharge processing operations. Generally, both an overlying and an underlying material, emit spectral signatures in the plasma. In one case, an endpoint is determined when the monitored intensity of the overlying layer species falls below a predetermined threshold level (indicating that the overlying layer is nearly fully etched away). In another case, when the monitored intensity of the underlying species rises above a preselected level (indicating that the underlying layer is nearly fully exposed), etching is terminated.
The methods set forth in the two patents described above are applicable to plasma etching. They are not applicable to chemical/mechanical polishing. Chemical/mechanical (chemi-mechanical, chem-mech) polishing is described in U.S. Pat. Nos. 4,671,851, 4,910,155, 4,944,836, all of which patents are incorporated by reference herein.
Generally, chem-mech polishing involves rubbing a wafer with a polishing pad in a slurry containing both an abrasive and chemicals. Typical slurry chemistry is KOH (Potassium Hydroxide), having a pH of about 11. A typical silica-based slurry is "SC-1"available from Cabot Industries. Another, more expensive slurry based on silica and cerium (oxide) is Rodel "WS-2000". When chemi-mechanical polishing is referred to hereinafter, it should be understood to be performed with a suitable slurry.
In many cases, chem-mech polishing can remove material at a greater rate than plasma etching. In any case, there is no plasma in which to monitor spectral content in order to determine the endpoint of chem-mech polishing.
U.S. Pat. No. 5,036,015, incorporated by reference herein, discloses a method of endpoint detection during chemical/mechanical planarization of semiconductor wafers. The endpoint is detected by sensing a change in friction between the wafer and the polishing surface (polishing pad). This change of friction may be produced when, for example, an (overlying) oxide coating on the wafer is removed and a harder or softer (underlying) material is contacted by the polishing surface. Friction is detected by monitoring the electric current supplied to motors rotating the wafer and the polishing surface.
Although the method described in U.S. Pat. No. 5,036,015 aptly identifies the need for detecting endpoint when chem-mech polishing, it does so in a rather "indirect" manner (sensing motor current) and assumes that the overlying material has a different coefficient of friction than the underlying material. Regarding the latter, the method will simply not work if the coefficients of friction of the overlying and underlying materials are not sufficiently different to allow detecting a change in friction. Further, the friction will change (e.g., increase or decrease) as the materials become more and more planar (e.g., more area being polished), and the slurry becomes depleted. Moreover, coefficients of friction are "mechanical" rather than "electrical" characteristics of a material, and are not of paramount concern in the selection of semiconductor materials. Additionally, the method of the patent would be defeated by changes in bearing friction, such as the motor bearings. Also, it is evident that the change in sensed friction between polishing away an overlying layer and exposing an underlying layer may be gradual, and extremely difficult to characterize, especially when "mountainous" topological features of the underlying layer are extending into the overlying layer and are becoming gradually exposed during polishing. Perhaps even more significantly, the technique of the patent is not suited to polishing a single, irregular layer since, in such a case, there would be no "overlying" layer with a different coefficient of friction than the underlying layer.
Moreover, chem-mech polishing is believed to be characterized by three distinct phases, each of which would introduce its own variables into the friction between pad and wafer. Namely:
1. Planarization: In a "Planarization Phase", only the highest parts of the top surface are removed.
2. Smoothing: In a "Smoothing Phase", all parts of the top surface are being polished back, but at different rates.
3. Blanket Polish Back: In a "Blanket Polish Back" phase, all parts of the top surface are removed at an equal rate.